1. Field of the Invention
The present invention relates to static semiconductor memory devices (hereinafter abbreviated as xe2x80x9cSRAMsxe2x80x9d) and, more particularly, to an SRAM capable of preventing soft errors.
2. Description of the Background Art
In recent years, semiconductor devices of portable apparatuses are required to operate at less energy and low voltage to provide longer battery life. Accordingly, the demand for SRAMs designed for low voltage operation with less power consumption has been on the increase. Such SRAMs for low voltage operation generally have six transistors and usually employ what is called a full CMOS (Complementary Metal-Oxide Semiconductor) memory cell.
FIG. 39 shows an equivalent circuit of a conventional SRAM memory cell. Referring to FIG. 39, a memory cell 100z of the SRAM includes n channel drive transistors 101 and 104, p channel load transistors 102 and 105, and n channel access transistors 103 and 106.
Memory cell 100z is connected to bit lines 171 and 172, a word line 199, a power supply node 175, and ground nodes 173 and 174. In memory cell 100z of the SRAM, drive transistors 101 and 104 as well as load transistors 102 and 105 form a flip flop circuit.
Load transistor 102 has its source region connected to power supply node 175 and drain region connected to a storage node 116. A gate electrode 111 of load transistor 105 is connected to a storage node 115.
Load transistor 105 has its source region connected to power supply node 175 and drain region connected to storage node 115. A gate electrode 112 of load transistor 105 is connected to storage nodes 116.
Drive transistor 101 has its source region connected to a ground node 173 and drain region connected to storage node 116. Gate electrode 111 of drive transistor 101 is connected to storage node 115.
Drive transistor 104 has its source region connected to a ground node 174 and drain region connected to storage node 115. Gate electrode 112 of drive transistor 104 is connected to storage node 116.
A gate electrode 113 of access transistor 103 is connected to word line 199. One of source and drain regions of access transistor 103 is connected to bit line 171, and the other connected to storage node 116.
Gate electrode 113 of access transistor 106 is connected to word line 199. One of source and drain regions of access transistor 106 is connected to bit line 172, and the other connected to storage node 115.
As shown in FIG. 39, memory cell 100z of the SRAM has an inverter formed by drive transistor 101 of an n channel transistor and a load transistor 102 of a p channel transistor. Further, it has an inverter formed by drive transistor 104 of an n channel transistor and load transistor 105 of a p channel transistor. These two inverters are combined and connected. An output of each inverter is an output of the other inverter, creating a stabilized state. These outputs are further connected to bit lines 171 and 172 through access transistors 103 and 106. When access transistors 103 and 106 are turned on, data are written to or read from bit lines 171 and 172.
In memory cell 100z shown in FIG. 39, when a potential at storage node 116 is relatively high, a potential at storage node 115 is relatively low. On the contrary, when the potential at storage node 116 is relatively low, the potential at storage node 115 is relatively high. These two states are used for storage of the presence of data.
FIG. 40 shows a plan view of the memory cell of the conventional SRAM shown in FIG. 39. Referring to FIG. 40, memory cell 100z of the SRAM includes a pair of load transistors 102 and 105, a pair of drive transistors 101 and 104, and a pair of access transistors 103 and 106.
Access transistor 103 has a pair of n-type impurity regions formed in an active region 130, and gate electrode 113. One of the impurity regions is connected to bit line 171 through contact hole 303, and the other connected to storage node 116 through a contact hole 302.
Access transistor 106 has a pair of n-type impurity regions formed in an active region 150, and gate electrode 113. One of the impurity regions is connected to bit line 172 through a contact hole 309, and the other connected to storage node 115 through a contact hole 206.
Drive transistor 101 has a pair of n-type impurity regions formed in active region 130, and gate electrode 111. One of the impurity regions is connected to ground node 173 through a contact hole 307, and the other connected to storage node 116 through contact hole 302.
Drive transistor 104 has a pair of n-type impurity regions formed in an active region 150, and gate electrode 112. One of the impurity regions is connected to ground node 174 through a contact hole 308, and the other connected to storage node 115 through contact hole 206.
Load transistor 102 has a pair of p-type impurity regions formed in an active region 140, and gate electrode 111. One of the impurity regions is connected to storage node 116 through a contact hole 301, and the other connected to power supply node 173 through a contact hole 305.
Load transistor 105 has a pair of p-type impurity regions formed in an active region 160, and gate electrode 112. One of the impurity regions is connected to storage node 115 through a contact hole 205, and the other connected to power supply node 175 through a contact hole 306.
FIG. 41 is a cross sectional view taken along the line XLIxe2x80x94XLI in FIG. 40. Referring to FIG. 40, an isolation oxide film 2 is formed above a silicon substrate 1. A p-type well region 107p and an n-type well region 108n are formed on the surface of silicon substrate 1. Active region 130 is formed in p-type well region 107p. Formed in p-type well region 107p are a pair of low-concentration impurity regions 131a and 131b as well as a pair of high-concentration impurity regions 132a and 132b, with each pair of regions being spaced apart from each other. Low-concentration impurity regions 131a, 131b and high-concentration impurity regions 132a, 132b form what is called an LDD (Lightly Doped Drain) structure. A channel dope region 133p of a p-type impurity region is formed between the pair of low-concentration impurity regions 131a and 131b. 
Gate electrode 113 is formed on silicon substrate 1 with a gate insulative film 113a interposed. A side surface of gate electrode 113 is covered with a sidewall oxide film 121 and an upper surface thereof is covered with an upper oxide film 122. Gate electrode 111 is formed on isolation oxide film 2. Gate electrode 111 is also covered with sidewall oxide film 121 and upper oxide film 122.
Active region 140 is formed in n-type well region 108n. Active region 140 has p type low-concentration impurity region 141a and p type high-concentration impurity region 142a. 
An interlayer insulative film 200 is formed to cover silicon substrate 1. Formed in interlayer insulative film 200 are contact holes 204, 203, 202, and 201, respectively reaching low-concentration impurity regions 131a, 131b, gate electrode 111, and low-concentration impurity region 141a. Plug layers 221 to 224 are respectively formed in contact holes 201 to 204. Pad electrodes 211, 212, and 213 are formed on interlayer insulative film 200 respectively to have contact with plug layers 221, 223, and 224. Storage node 115 is formed on interlayer insulative film 200 to have contact with plug layer 222.
An interlayer insulative film 300 is formed to cover interlayer insulative film 200. Formed in interlayer insulative film 303 are contact holes 301, 302, and 303, respectively reaching pad electrodes 211, 212, and 213. Plug layers 321 to 323 are respectively formed in contact holes 301 to 303. Storage node 116 is formed to have contact with plug layers 321 and 322. Bit line 171 and power supply node 175 are formed on interlayer insulative film 300.
Memory cells may suffer from a so-called a soft error phenomenon, where radiation is directed from radioactive elements contained in a package or the like, thereby causing data loss. For a DRAM (Dynamic Random Access Memory), for example, it is known that electric charges accumulated in a capacitor are neutralized by those generated by xcex1 rays, thereby causing data loss. It is also known that the above mentioned SRAM suffers from the soft error phenomenon where a stored content is inverted by electric charges caused by xcex1 rays. Particularly in recent years, miniaturization of semiconductor devices tends to reduce the amount of electric charges to be accumulated, whereby the devices are more likely to be subjected to data inversion.
FIG. 42 is a diagram shown in conjunction with the problem of the conventional SRAM. Referring to FIG. 42, when ax rays are externally directed to the memory cell of the SRAM in the direction indicated by an arrow 220, these xcex1 rays produce electrons 10e and holes 10h in silicon substrate 1. Here, assume that electric charges are accumulated in storage node 116 and the potential at storage node 116 is relatively high. In this state, if xcex1 rays are directed in the direction indicated by arrow 220, electrons 10e and holes 10h are produced in silicon substrate 1. The produced electrons move to high-concentration impurity region 132b with relatively high potential, whereby the potential at the high-concentration impurity region 132b becomes relatively low. Consequently, the potential at storage node 116 becomes relatively low, whereby the potential at the storage node 116 is inverted to what is called Vss potential. Thus, the problem associated with the soft error of data loss arises.
Therefore, the present invention is made to solve the aforementioned problems. An object of the present invention is to provide a static semiconductor memory device capable of preventing soft errors despite of its miniaturized structure.
A static semiconductor memory device according to one aspect of the present invention includes a semiconductor substrate, a storage node, an impurity region of a second conductivity type, and an impurity region of a first conductivity type. The semiconductor substrate has a semiconductor region of the first conductivity type. The storage node is formed on the semiconductor substrate. The impurity region of the second conductivity type is formed on a surface of the semiconductor region and electrically connected to the storage node. The impurity region of the first conductivity type is formed in the semiconductor region to have contact with the impurity region of the second conductivity type.
In thus formed static semiconductor memory device, the impurity region of the second conductivity type electrically connected to the storage node and the impurity region of the first conductivity type are formed in contact with each other, so that the impurity regions of the second and first conductivity types have capacitances. Accordingly, electric charges accumulated in the impurity region of the second conductivity type and the storage node attract those of the opposite conductivity type in the impurity region of the first conductivity type, whereby loss of electric charges accumulated in the impurity region of the second conductivity type is prevented. As a result, inversion of the stored information is less likely to occur and the problem associated with the soft errors can be prevented.
A static semiconductor memory device according to another aspect of the present invention includes a semiconductor substrate, a storage node, a field effect transistor, and a pair of impurity regions of a first conductivity type. The semiconductor substrate has a semiconductor region of the first conductivity type. The storage node is formed on the semiconductor substrate. The field effect transistor is formed in the semiconductor region. The field effect transistor includes a gate electrode and a pair of source and drain regions. The gate electrode is formed on the semiconductor region with a gate insulative film interposed. The pair of source and drain regions is formed in the semiconductor region on both sides of the gate electrodes and formed of impurity regions of a second conductivity type. One of the pair of source and drain regions is electrically connected to the storage node. The pair of impurity regions of the first conductivity type is positioned under the source and drain regions. An impurity concentration of the pair of impurity regions of the first conductivity type is higher than that of a region between the pair of impurity regions of the first conductivity type.
In the static semiconductor memory device having the above-described structure, the impurity region of the first conductivity type is formed under the source and drain regions electrically connected to the storage node. Thus, the impurity region of the first conductivity type and the source and drain regions of the impurity region of the second conductivity type have capacitances. As a result, electric charges accumulated in the storage node and the source and drain regions attract electric charges of the opposite conductivity type in the impurity region of the first conductivity type, so that loss of electric charges is prevented. Consequently, inversion of stored information is less likely to occur and the problem associated with so-called soft errors can be prevented.
Further, in the region positioned below the source and drain regions, the concentration of the pair of impurity region of the first conductivity type is higher than that of the impurity region of the first conductivity type positioned therebetween. Thus, the impurity region of the first conductivity type and the source and drain regions have greater coupling capacitance. Between the pair of impurity regions of the first conductivity type, i.e., below the gate electrode, the impurity concentration of the first conductivity type is low enough not to affect the channel region. As a result, a threshold value of the field effect transistor would not change.
A static semiconductor memory device according to still another aspect of the present invention includes a semiconductor substrate and a storage node. The storage node is formed on the semiconductor substrate. The storage node has a first storage node portion extending in a prescribed direction, and a second storage node portion formed opposite to and on the first storage node portion with a dielectric material interposed and extending in the same direction as the first storage node portion.
In the static semiconductor memory device having the above-described structure, the storage node has the first and second storage node portions, which are formed opposite to each other with the dielectric material interposed. Thus, the first and second storage node portions have capacitances. As a result, electric charges accumulated in one of the first and second storage node portions attract those of the opposite conductivity type of the other, so that loss of electric charges accumulated in the storage node can be prevented. Therefore, the problem associated with soft errors would not arise. Further, since the second storage node portion extends in the same direction as the first storage node portion, the first and second storage node portions are arranged opposite to each other over a greater area. As a result, soft errors can be prevented more effectively.
Preferably, the static semiconductor memory device further includes a region with substantially constant potential formed in the semiconductor substrate. The first storage node portion is electrically connected to the region with substantially constant potential. In this case, the potential at the first storage node remains substantially constant, so that the potential at the second storage node can be more stabilized as compared with the case where the potential at the first storage node varies. Thus, it is ensured that electric charges are accumulated in the second storage node.
More preferably, the first storage node portion is formed over almost entire region of the second storage node portion when viewed from above. Then, in particular, the first and second storage node portions are arranged opposite to each other over a greater area, so that the coupling capacitance of the first and second storage node portions increases. As a result, soft errors can be prevented more effectively.
More preferably, the static semiconductor memory device further includes a load transistor and a drive transistor. The storage node is a gate electrode of the load or drive transistor.
More preferably, the static semiconductor memory device further includes a pair of drive transistors. The storage node electrically connects the gate electrode of one drive transistor and the drain region of the other drive transistor.
A static semiconductor memory device according to still another aspect of the present invention includes a semiconductor substrate, a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type, and a field effect transistor. The semiconductor region of the first conductivity type is formed in the semiconductor substrate. The semiconductor region of the second conductivity type is formed in the semiconductor substrate to have contact with the semiconductor region of the first conductivity type. The field effect transistor has a channel region of the first conductivity type formed in the semiconductor region of the first conductivity type. The semiconductor region of the second conductivity type is in contact with the semiconductor region of the first conductivity type and includes a first extension region extending toward the channel region.
In the static semiconductor memory device having the above-described structure, the second semiconductor region has the first extension region extending toward the channel region, so that any carriers caused by xcex1 rays near the channel region can be absorbed into the first extension region. As a result, the storage node connected to the semiconductor region of the first conductivity type would not be adversely affected by the carriers. Consequently, soft errors can be prevented.
More preferably, a potential different from that of the semiconductor region of the first conductivity type is applied to the semiconductor region of the second conductivity type to attract carriers of the second conductivity type. In this case, even if carriers of the second conductivity type are caused in the semiconductor region of the first conductivity type, these carriers of the second conductivity type are attracted from the semiconductor region of the first conductivity type to the semiconductor region of the second conductivity type through the first extension region. As a result, the carriers of the second conductivity type would not adversely affect the transistor formed in the semiconductor region of the first conductivity type. Consequently, soft errors can be more reliably prevented.
More preferably, the semiconductor region of the second conductivity type further includes a second extension region covering the semiconductor region of the first conductivity type. Then, the second extension region surrounds the semiconductor region of the first conductivity type, so that soft errors can be prevented more effectively.
A static semiconductor memory device according to still another aspect of the present invention includes a semiconductor substrate, a gate electrode, a sidewall dielectric film, source and drain regions, and a conductive layer. The gate electrode is formed on the semiconductor substrate with a gate insulative film interposed and electrically connected to a storage node. The sidewall dielectric film is formed to be in contact with the sidewall of the gate electrode. The source and drain regions are formed on the semiconductor substrate on both sides of the gate electrode. The conductive layer is connected to one of the source and drain regions and formed on the gate electrode with the sidewall dielectric film interposed.
In the static semiconductor memory device having the above-described structure, the conductive layer is formed on the gate electrode with the sidewall insulative film interposed, so that the conductive layer and the gate electrode have capacitances. Since the gate electrode is electrically connected to the storage node, electric charges accumulated in the storage node and the gate electrode attract electric charges of the opposite conductivity type in the conductive layer. As a result, loss of electric charges accumulated in the storage node and gate electrode can be prevented. Thus, soft errors are prevented.
More preferably, the potential of the conductive layer remains substantially constant. Then, electric charges can be accumulated stably in the gate electrode and the storage node.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.